1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a variable resistance memory device, and more particularly, to a method for fabricating a variable resistance memory device having a cross point cell array structure.
2. Description of the Related Art
A variable resistance memory device is a data storage device that uses characteristics of switching between at least two different resistance states by varying resistance according to external stimuli. Exemplary variable resistance memory devices include a resistive random access memory (ReRAM), a phase change RAM (PCRAM), a spin transfer torque-RAM (STT-RAM), etc.
According to an example, a ReRAM includes a variable resistance layer made of variable resistance materials, such as Perovskite-based materials or transition metal oxides, and electrodes on both sides of the variable resistance layer. Using this structure, a filament current path within the variable resistance layer is formed or removed according to a voltage applied to the electrodes. Here, the variable resistance layer is in a low resistance state when the filament current path is generated and is in a high resistance state when the filament current path is removed. According to an example, switching from the high resistance state to the low resistance state is referred to as a set operation, while switching from the low resistance state to the high resistance state is referred to as a reset operation.
Meanwhile, in order to improve integration of the variable resistance memory device, a so-called cross point cell array structure has been proposed. Hereinafter, a process for fabricating the variable resistance memory device having the cross point cell array structure in accordance with the related art will be described.
FIG. 1 is a circuit diagram of a variable resistance memory device having a cross point cell array structure, and FIG. 2 is a diagram schematically illustrating a structure in which the variable resistance memory device of FIG. 1 forms a stacked, multilayer structure.
Referring to FIG. 1, memory cells (MCs) are disposed at each intersecting point among a plurality of bit lines (BLs) and a plurality of word lines WL intersecting the plurality of bit lines (BLs). In this configuration, each memory cell (MCs) includes variable resistance elements of which the resistance varies according to applied voltages and the like. The structure of the cross point cell array is a stacked, multilayer structure (see FIG. 2) to improve integration of the memory cells (MCs).
FIGS. 3A to 3B are plan views for illustrating a method for fabricating a conventional variable resistance memory device, and FIG. 4 is a cross-sectional view illustrating an arrangement of a memory cell of the conventional variable resistance memory device.
Referring to FIG. 3A, after the plurality of word lines (WLs) extending in one direction are formed, bottom electrodes (BEs) arranged in an island shape are formed on the word lines (WLs) at a designated interval. Subsequently, the variable resistance layers (MCs) are formed on the bottom electrode (BE).
Referring to FIG. 3B, after top electrodes (TEs) are formed on the variable resistance layers (MCs), the plurality of bit lines (BLs) extending in a direction intersecting the word lines (WLs) while contacting the top electrodes (TEs) are formed.
Referring to FIG. 4, the cross point cell array structure may be formed as a multilayer structure by repeatedly performing the fabricating process described above. However, the bottom electrodes (BEs), the memory cells (MCs), and the top electrodes (TEs) are each formed by a separate patterning, where a misalignment between top and bottom layers may occur and cause a sudden increase in contact resistance. In addition, the fabricating process is complicated and the fabricating cost is increased, due to the repetition of the plurality of mask processes.